Digital-to-analog converters (DACs) have been utilized in the past for such applications as frequency division multiplexing (FDM) telephony, professional audio and a wide variety of other applications in which digital signals are to be converted into their analog counterpart. When digital signals are clocked into the converter at a predetermined rate, the output signal from the digital-to-analog converter is an analog replica of the digital signal. For most digital-to-analog converters, the analog voltages or currents, are developed by so-called current sources which are resistor controlled. The conventional resistor matrix, which is utilized in the generation of the analog currents or voltages, is a so-called R, 2R network, which is configured so as to be able to accommodate a binary input code which controls switches which connect various resistors in a network from a voltage reference source to an output bus. The output currents are thus binary weighted, so that the R, 2R network is one-to-one compatible with the binary number coding system. The result of proper combining of the binary weighted currents is a system which produces linear incremental voltage steps for incremental number increases in the binary input code.
There are essentially two major problems with the R, 2R digital-to-analog converters. The first problem is the accuracy to which a digital input code can be converted to an analog voltage. This accuracy depends very heavily on the tolerances of the resistive elements in the resistor matrix. In an R, 2R network, the tolerance is not merely the tolerance of a single resistive element, but rather the combined tolerance of many series/parallel connected resistive elements since the R, 2R network operates with series/parallel combinations of resistive elements. Thus, for instance, to achieve a 0.0008% tolerance in the output voltage for a 16 bit DAC, at least one resistive element must have a tolerance of 0.0016%. Note, that 0.0016% tolerances are almost impossible to achieve in the present state of the art.
The second problem with the R, 2R network is that due to the binary switching system, transients occur when various transistors switch from one state to another in accordance with a change in input code. These transients are called "glitches" which bespeaks their undesirability and is a problem which has plagued digital-to-analog converters since their inception.
When utilizing R, 2R networks, the glitch is generated because of the difference in switching times to turn a transistor ON versus the time it takes to switch it OFF. In an R, 2R network going from one code to another, it is often times necessary to turn one switch ON while "simultaneously" turning another switch OFF. In matter of fact, because switches do not turn ON as fast as they turn OFF, one cannot "simultaneously" turn one switch OFF and another ON or vice versa. The result is that the output voltage of the digital-to-analog converter momentarily swings towards 0 volts or full maximum during the time period in which the switches are not acting "simultaneously." In summary, for an R, 2R network, there will always be transitions in the input code which will result in some of the switches being turned OFF while some of the switches are being turned ON. Due to the differential in the reaction times of the switches depending on which direction they are switching, transients result which are extremely annoying and detrimental especially when the output of the digital-to-analog converter is utilized to drive a cathode ray tube.
Some applications can forgive this shortcoming. But when digital-to-analog converters are utilized to drive the beam deflection circuits of a cathode ray tube (CRT) graphic display system, distortion caused by glitches, is easy to see and more than just annoying. Converters used for this purpose must have short settling times and high current drive capability in addition to producing a low glitch level. Rapid settling is vital to flicker-free display of complex patterns. In general to avoid flicker, the converter must be able to update at about 10 MHz or faster.
While many current state of the art digital-to-analog converters can provide the fast settling and high current output needed to drive cathode ray tubes, a low glitch level has remained elusive. De-glitching techniques in the past have involved the use of sample and hold circuitry which is normally operated in the track mode and is switched to the hold mode just before the converter is updated. When the converter has settled to the new value, the sample and hold is switched back to the track mode. Thus the glitch period is effectively isolated from the output.
Of course, to be effective, the sample and hold circuit itself should not introduce significant voltage spikes at the output. In addition to the costs of the sample and hold circuit which can be as high as that of a converter of comparable speed and resolution, this technique introduces extra delay due to the sample and hold acquisition time. This usually limits the update rate to two MHz or less. Additional error from sample and hold offset and "droop" can be expected.
Another anti-glitching technique useful for graphic display systems that can tolerate a lower converter update rate is a bandwidth or slew rate limited circuit. In one example of such a de-glitching system, a balanced diode bridge is utilized in which any fast changing signal-like glitches are filtered out. Unfortunately, this increases a converter's overall response time, thus reducing the ability of the converter to operate at high frequencies.
In another conventional de-glitching technique, multiplying converters are used to circumvent glitch problems in CRT graphic display systems. A multiplying converter's analog output is proportional to the product of a variable reference and the input code. In a typical setup, a pair of current-output converters drive each CRT input (X deflection and Y deflection). The two fixed-reference converters determine the position of a starting point of the display line. Their outputs are summed with the external variable-resistance (multiplying) digital-to-analog converters, which are driven by a 0 to 10 volt ramp reference. The ratio and magnitude of the multiplying units digital codes, determine the slope and length respectively of the line being generated on the display. Complex display characters are made up of a series of these straight lines. Since glitches occur only when the converter input codes are changing, this step minimizes the code updating as the beam is essentially being driven by the ramp. In addition, the input codes can be changed during the retrace of the beam when the screen is usually blanked.
While this method offers a solution to the glitch problem in a CRT display system, its most obvious limitation is the cost of two extra converters. Moreover, the updating logic is more complex, as four converters must be updated instead of two. Finally, only one straight line segment may be drawn per sweep, so that in a complex character generating system, where many such segments are required, the devices must have a very fast settling time, 100 nanoseconds or less.